Keynote Microprocessor Architectures for the Mobile Internet Era
The mobile Internet era is characterized by three core technology trends: First, wireless bandwidth growth is outpacing Moore’s Law by an order of magnitude. Second, Moore’s Law itself is becoming constrained, as continuously increasing chip transistor densities lead to prohibitive heat density levels. And third, mobility, anytime, anyplace and on any device, is rapidly becoming a key design requirement, calling for smart, energy-aware placement of transistors across the network.
In the periphery of the Internet, these trends culminate in ubiquitous Internet appliances that deliver dynamic content over persistent realtime connections. Their requirements define the design imperatives of future Internet microprocessors: high integration— to minimize form factors; high energy efficiency— to maximize battery life or computational density; compatibility— with the full PC and Internet experience; and flexibility— to quickly adapt to new devices, content types and usage models.
The Crusoe microprocessor is an example for how these design imperatives can be realized. It uses a hybrid hardware/software architecture. The hardware consists of a highly efficient VLIW core, which is complemented by the Code Morphing Software. The latter currently implements the x86 instruction set and a Java Virtual Machine. This architecture can be extended into a self-optimizing, largely instruction set agnostic, “soft” core.