4. On-line Check Technology for Processor Control Signals

  • Matthias Pflanz
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2270)


An obvious problem is the case of faulty control signals for fault-free components. Encoding and/or prediction techniques for component checks are useless if the wrong function is observed. Controller faults are to be seen in connection with an error latency. It leads often to exceptions, whereby the time of fault occurrence is rarely identifiable. Therefore, a large number of strategies was proposed for control flow check in processors. Mostly used techniques are based on signature analysis [61],[62], [35], [63]. For instance in [35], a special watchdog circuit is able to observe control flow signatures. Hellebrand and Wunderlich have proposed methods that perform controller error detection in the next clock cycle based on feedback shift registers and signature analysis [64]. These and similar techniques are in most cases combined with an error detection latency due to the analysis with shift registers. Because this delay doesn’t allow fast recovering strategies like a micro-rollback, an on-line error detection within the same clock cycle is strongly necessary.


Control Logic State Encode Prediction Unit Embed Processor Error Part 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Matthias Pflanz
    • 1
  1. 1.Department of Processor Development IIIBM Deutschland Entwicklung GmbHBöblingenGermany

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