2. Fault Models and Fault-Behavior of Processor Structures

  • Matthias Pflanz
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2270)


During the process of specification, design and implementation of an embedded system, various types of faults are possible. Fig. 4 outlines the according fault parts during the whole development process:

In this thesis, specification or design faults are not addressed. Faults which arise from the manufacturing process can be classified as follows: Signal line faults can be break (a signal line or a contact is interrupted) or bridge (Signal lines are unintentionally connected). A strong short of a signal line with GND (stuck-at-0), with VDD (stuck-at-1) or with another signal line (line bridge) is a ‘hard’ bridge fault - respective a permanent fault. On the other hand, a high-impedance bridge or a pinhole connection between lines may cause a dynamic fault, e.g. by an increased gate- or pathdelay. These effects can be assigned to parametric faults. Transistor faults are often caused by parametric faults. In MOS (Metal-Oxide-Semiconductor) transistor circuits, the silicon oxide is used as an insulation material and as the gate oxide. Therefore, oxide faults are a common reason for transistor failures. If the gate oxide is too thin, for instance, the transistor is susceptible to permanent gate damage by voltage peaks. Also, material pollution is possible. Here, mobile ions can exist under high-voltage condition which may be accumulated near the gate and cause a shift of the transistor threshold voltage.


Fault Model Signal Line Control Word Latent Error Transient Fault 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Matthias Pflanz
    • 1
  1. 1.Department of Processor Development IIIBM Deutschland Entwicklung GmbHBöblingenGermany

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