Processor Pipelines and Their Properties for Static WCET Analysis

  • Jakob Engblom
  • Bengt Jonsson
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2491)


When developing real-time systems, the worst-case execution time (WCET) is a commonly used measure for predicting and analyzing program and system timing behavior. Such estimates should preferrably be provided by static WCET analysis tools. Their analysis is made difficult by features of common processors, such as pipelines and caches.

This paper examines the properties of single-issue in-order pipelines, based on a mathematical model of temporal constraints. The key problem addressed is to determine the distance (measured in number of subsequent instructions) over which an instruction can affect the timing behavior of other instructions, and when this effect must be considered in static WCET analysis. We characterize classes of pipelines for which static analysis can safely ignore effects longer than some arbitrary threshold. For other classes of pipelines, pipeline effects can propagate across arbitrary numbers of instructions, making it harderto design safe and precise analysis methods.

Based on our results, we discuss how to construct safe WCET analysis methods. We also prove when it is correct to use local worst-case approximations to construct an overall WCET estimate.


Execution Time Critical Path Data Dependence Constraint System Pipeline Stage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    ARM Ltd. ARM 9TDMI Technical Reference Manual, 3rd edition, March 2000. Document no. DDI0180A.Google Scholar
  2. 2.
    P. Atanassov, R. Kirner, and P. Puschner. Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis. In Proc. IEEE Real-Time Embedded Systems Workshop, held in conjunction with RTSS 2001, December 2001.Google Scholar
  3. 3.
    I. Bate, G. Bernat, G. Murphy, and P. Puschner. Low-level Analysis of a Portable Java Byte Code WCET Analysis Framework. In Proc. 7 th International Conference on Real-Time Computing Systems and Applications (RTCSA’00), pages 39–48. IEEE Computer Society Press, December 2000.Google Scholar
  4. 4.
    A. Colin and I. Puaut. A Modular and Retargetable Framework for Tree-Based WCET Analysis. In Proc. 13 th219 Euromicro Conference on Real-Time Systems, (ECRTS’ 01). IEEE Computer Society Press, June 2001.Google Scholar
  5. 5.
    Rina Dechter, Itay Meiri, and Judea Pearl. Temporal constraint networks. Artifical Intelligence, 49:61–95, 1991.zbMATHCrossRefMathSciNetGoogle Scholar
  6. 6.
    J. Engblom. Processor Pipelines and Static Worst-Case Execution Time Analysis. PhD thesis, Dept. of Information Technology, Uppsala University, April 2002. Acta Universitatis Upsaliensis, Dissertations from the Faculty of Science and Technology 36,
  7. 7.
    J. Engblom and A. Ermedahl. Pipeline Timing Analysis Using a Trace-Driven Simulator. In Proc. 6 th International Conference on Real-Time Computing Systems and Applications (RTCSA’99). IEEE Computer Society Press, December 1999.Google Scholar
  8. 8.
    C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm. Reliable and Precise WCET Determination for a Real-Life Processor. In Proc. First International Workshop on Embedded Software (EMSOFT 2001), LNCS 2211. Springer-Verlag, October 2001.Google Scholar
  9. 9.
    C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), January 1999.Google Scholar
  10. 10.
    J. Heinrich. MIPS R4000 Microprocessor User’s Manual. MIPS Technologies Inc., 2 nd edition, 1994.Google Scholar
  11. 11.
    J. L. Hennessy and D. A. Patterson. Computer Architecture A Quantitative Approach. Morgan Kaufmann Publishers Inc., 2 nd edition, 1996. ISBN 1-55860-329-8.Google Scholar
  12. 12.
    Hitachi Europe Ltd. SH7700 Series Programming Manual, September 1995.Google Scholar
  13. 13.
    Infineon. Instruction Set Manual for the C1 66 Family, 2nd edition, March 2001.Google Scholar
  14. 14.
    S.-S. Lim, Y. H. Bae, C. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, K. Park, and C. S. Ki. An Accurate Worst-Case Timing Analysis for RISC Processors. IEEE Transactions on Software Engineering, 21(7):593–604, July 1995.Google Scholar
  15. 15.
    S.-S. Lim, J. H. Han, J. Kim, and S. L. Min. A Worst Case Timing Analysis Technique for Multiple-Issue Machines. In Proc. 19 th IEEE Real-Time Systems Symposium (RTSS’98), December 1998.Google Scholar
  16. 16.
    T. Lundqvist and P. Stenström. Timing Anomalies in Dynamically Scheduled Microprocessors. In Proc. 20 th IEEE Real-Time Systems Symposium (RTSS’99), December 1999.Google Scholar
  17. 17.
    NEC Corporation. V850 Family 32/16-bit Single Chip Microcontroller User’s Manual: Architecture, 4th edition, 1995. Document no. U10243EJ4V0UM00.Google Scholar
  18. 18.
    NEC Corporation. V850E/MS1 32/16-bit Single Chip Microcontroller: Architecture, 3rd edition, January 1999. Document no. U12197EJ3V0UM00.Google Scholar
  19. 19.
    G. Ottosson and M. Sjödin. Worst-Case Execution Time Analysis for Modern Hardware Architectures. In Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems (LCT-RTS’97), June 1997.Google Scholar
  20. 20.
    Jörn Schneider and Christian Ferdinand. Pipeline Behaviour Prediction for Superscalar Processors by Abstract Interpretation. In Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES’99), May 1999.Google Scholar
  21. 21.
    Friedhelm Stappert. Predicting pipelining and caching behaviour of hard real-time programs. In Proc. of the 9 th Euromicro Workshop on Real-Time Systems IEEE Computer Society Press, June 1997.Google Scholar
  22. 22.
    D. Ziegenbein, F. Wolf, K. Richter, M. Jersak, and R. Ernst. Interval-Based Analysis of Software Processes. In Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES’2001), June 2001.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Jakob Engblom
    • 1
  • Bengt Jonsson
    • 1
  1. 1.Dept. of Information TechnologyUppsala UniversityUppsalaSweden

Personalised recommendations