Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI

Abstract

The KASUMI block cipher and the confidentiality (f8) and integrity (f9) algorithms using KASUMI in feed back cipher modes have been standardized by the 3GPP. We designed compact and high-speed implementations and then compared several prototypes to existing designs in ASICs and FPGAs. Making good use of the nested structure of KASUMI, a lot of function blocks are shared and reused. The data paths of the f8 and f9 algorithms are merged using only one 64-bit selector. An extremely small size of 3.07 Kgates with a 288 Mbps throughput is obtained for a KASUMI core using a 0.13- μm CMOS standard cell library. Even simultaneously supporting both the f8 and f9 algorithms, the same throughput is achieved with 4.89 Kgates. The fastest design supporting the two algorithms achieves 1.6 Gbps with 8.27 Kgates.