Abstract
In hard real-time systems, the worst-case execution times of programs must be known. Obtaining safe upper bounds for these times by measuring actual executions is rarely possible, since the worst case input is normally not known. We apply static program analysis methods to determine an upper bound for the WCET. While this approach is not new, we believe to be the first to have developed a tool that implements these techniques for all the features of a real-life, non-trivial processor, the Motorola ColdFire 5307. Our tool is, to the best of our knowledge, the first one that can determine a safe and rather precise WCET bound for a processor that has caches and pipelines and performs branch prediction and instruction prefetching.
Our approach to use a pipeline model in the analysis of the processor behavior opens up new perspectives towards a generative analysis approach and can prove helpful in investigating other processor properties. The emphasis of this paper is on the modeling of the pipeline behavior as input to the derivation of a pipeline analysis.
This work was partly supported by the RTD project IST-1999-20527 DAEDALUS of the European FP5 program.
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Langenbach, M., Thesing, S., Heckmann, R. (2002). Pipeline Modeling for Timing Analysis. In: Hermenegildo, M.V., Puebla, G. (eds) Static Analysis. SAS 2002. Lecture Notes in Computer Science, vol 2477. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45789-5_22
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