Abstract
Control flow monitoring using a watchdog processor is a well- known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor instruction stream creating noticeable memory and performance overheads. A novel watchdog processor architecture using embedded signatures is presented that minimizes the memory overhead and nullifies performance penalty on the main processor without sacrificing error detection coverage or latency. This scheme is called Interleaved Signature Instruction Stream (ISIS) in order to reflect the fact that signatures and main instructions are two independent streams that co-exist in the system.
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Rodríguez, F., Campelo, J.C., Serrano, J.J. (2002). A Watchdog Processor Architecture with Minimal Performance Overhead. In: Anderson, S., Felici, M., Bologna, S. (eds) Computer Safety, Reliability and Security. SAFECOMP 2002. Lecture Notes in Computer Science, vol 2434. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45732-1_26
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DOI: https://doi.org/10.1007/3-540-45732-1_26
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