Abstract
In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we propose a simple heuristic model that includes its dependence on the output load and the input transition time. We have tested this model and found a mean deviation lower than 4%. Also, we present a characterization process for this model that is fully integrated into AUTODDM without affecting the total simulation time needed to characterize a standard cell.
This work has been partially supported by the MCYT MODEL project TIC 2000- 1350 and MCYT VERDI project TIC 2002-2283 of the Spanish Government.
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Millán, A., Juan, J., Bellido, M.J., Ruiz-de-Clavijo, P., Guerrero, D. (2002). Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_48
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DOI: https://doi.org/10.1007/3-540-45716-X_48
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