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Probabilistic Power Estimation for Digital Signal Processing Architectures

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2451))

Abstract

A method for estimating the power on architecture-level is described. Originally based on simulations with data sequences, the method is extended by an simulation-free approach. The statistical properties required for the underlying Dual-Bit-Type model are propagated through the circuit. The necessary computation formulas are presented. For both approaches, the model accuracy for base modules as for signal processing applications is comparably low.

The work presented is supported by the German Research Foundation, Deutsche Forschungsgemeinschaft (DFG), within the research initiative “VIVA” under contract number PI 169/14.

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References

  1. W.-H. Chen, H. Smith, and S. C. Fralick. A fast computational algorithm for the discrete cosine transform. IEEE Transactions on Communications, 25(9):1004–1009, Sept. 1977.

    Article  MATH  Google Scholar 

  2. A. Freimann. Framework for high-level power estimation. In D. Soudris, P. Pirsch, and E. Barke, editors, Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation (PATMOS), 10th InternationalWorkshop, volume 1918 of Lecture Notes in Computer Science, pages 56–65, Heidelberg, Sept. 2000. Springer Verlag.

    Google Scholar 

  3. S. Gupta and F. N. Najm. Power modeling for high level power estimation. In ACM/IEEE Design Automation Conference, pages 365–370, 1997.

    Google Scholar 

  4. P. E. Landman and J. M. Rabaey. Architectural power analysis: The dual bit type method. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(2):173–187, June 1995.

    Article  Google Scholar 

  5. C. Loeffler, A. Ligtenberg, and G. S. Moschytz. Practical fast 1-d dct algorithms with 11 multiplications. In IEEE International Conference on Acoustics, Speech, and Signal Processing, volume II, pages 988–991, 1989.

    Google Scholar 

  6. Synopsys, Inc. DesignWare Foundation Quick Reference Guide, V2000.11, 2000.

    Google Scholar 

  7. J. Zhang and N.W. Bergmann. A new 8X8 fast dct algorithm for image compression. In IEEE Workshop on Visual Signal Processing and Communications, pages 57–60, Sept. 1993.

    Google Scholar 

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© 2002 Springer-Verlag Berlin Heidelberg

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Freimann, A. (2002). Probabilistic Power Estimation for Digital Signal Processing Architectures. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_46

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  • DOI: https://doi.org/10.1007/3-540-45716-X_46

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44143-4

  • Online ISBN: 978-3-540-45716-9

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