Abstract
This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.
This work has been partially supported by the MCYT MODEL project TIC 2000- 1350 and MCYT VERDI project TIC 2002-2283 of the Spanish Government.
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Ruiz-de-Clavijo, P., Juan, J., Bellido, M.J., Millán, A., Guerrero, D. (2002). Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_40
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DOI: https://doi.org/10.1007/3-540-45716-X_40
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