Abstract
Power consumption is becoming a major issue for embedded systems design. High power consumption reduces battery life and affects system cost and performances. This paper introduces a new power reduction technique that combines an asynchronous processor and a low power operating system (OS). The asynchronous processor is ideal for embedded applications: it is low power and functional within a wide supply voltage range. According to the tasks requirements, the OS regulates the processor operating voltage and so the computational power at run-time. This ensures minimum energy consumption. Simulation results show that low power OS— asynchronous processor combination reduce drastically power consumption in a real-time embedded system.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Pedram, M.: Design Technologies for Low Power VLSI. In: Encyclopedia of Computer Science and Technology, Vol. 36. Marcel Dekker, Inc., (1997) 73–96
Benini, L., Bogliolo, A., De Micheli, G.: A Survey of Design Techniques for System-Level Dynamic Power Management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, N° 3, (June 2000) 299–316
Mudge, T.: Power: A First-Class Architectural Design Constraint. IEEE Computer, (2001) 52–58
Gowan, M.K., Biro, L.L., Jackson, D.B.: Power Considerations in the Design of the Alpha 21264 Microprocessor. 35th Design Automation Conference, San Francisco, CA USA (1998) 726–731
Nielsen, L.S., Niessen, C., Sparso, J., Van Berkel, J.: Low Power Operation Using Self-Timed Circuits and Adaptative Scaling of the Supply Voltage. In: IEEE Transaction on Very large Scale Integration (VLSI) Systems, Vol. 2, N°4, (December 1994)
Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low Power CMOS Digital Design. In: IEEE Journal of Solid-State Circuits, Vol. 27, N° 4, (April 1992) 473–484
Burd, T., Brodersen, R.W.: Energy Efficient CMOS Microprocessor Design. Proc. 28th Hawaï Int’l Cof. on System Sciences, Vol. 1, (Jan 1995) 288–297
Smit, G.J.M., Havinga, P.J.M.: A survey of energy saving techniques for mobile computers. Moby Dick technical report (1997) http://www.cs.utwente.nl/~havinga/papers/energy.ps
Simunic, T., Benini, L., Acquaviva, A., De Micheli, G.: Dynamic Voltage Scaling for Portable Systems. 38th Design Automation Conference, Las Vegas (18–22 June 2001) 524–529
Lu, Y.H., Benini, L., De Micheli, G.: Operating-System Directed Power Reduction. ISLPED’00, Rapallo, Italy (2000) 37–42
Lu, Y.H., De Micheli, G.: Comparing System-Level Power Management Policies. IEEE Design & test of Computers, (2001) 10–19
Srivasta, M.B., Chandrakasan, A.P., Brodersen, R.W.: Predictive System Shutdown and Other Architectural Techniques for Energy Effcicient Programmable Computation. IEEE Transactions on very Large Scale Integration (VLSI) Systems, Vol. 4, N°1, (March 1996) 42–55
Flautner, K.: Automatic Monitoring for Interactive Performance and Power Reduction. Dissertation, Michigan University (2001)
Pering, T., Burd, T., Broderesen, R.: Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System. In: Power-Driven Microarchitecture Workshop, in conjunction with Intl. Symposium on Computer Architecture, Barcelona, Spain, (June 1998)
Weiser, M., Welch, B., Demers, A., Shenker, S.: Scheduling for reduced CPU energy. In: USENIX Symposium on Operating Systems Design and Implementation, (1994) 13–25
Govil, K., Chan, E., Wassermann, H.: Comparing algorithms for dynamic speed-setting of a low-power CPU. In: ACM International Conference on Mobile Computing and Networking, (1995) 13–25
Pering, T., Burd, T., Brodersen, R.: Voltage Scheduling in the lpARM Microprocessor System. ISLPED’ 00, Rapallo, Italy (2000) 96–101
Kumar, P., Srivastava, M.: Predictive Strategies for Low-Power RTOS Scheduling. IEEE (2000) 343–348
Renaudin, M., Vivet, P., Robin, F.: ASPRO: an Asynchronous 16-Bit RISC Microprocessor with DSP Capabilities. ESSCIRC 99, Duisburg, Germany, (21–23 Sept.1999) 28–31
Renaudin, M., Vivet, P., Robin, F.: ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor. Proc. of the Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE (1998) 22–23
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Salhiene, M.E., Fesquet, L., Renaudin, M. (2002). Dynamic Voltage Scheduling for Real Time Asynchronous Systems. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_39
Download citation
DOI: https://doi.org/10.1007/3-540-45716-X_39
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44143-4
Online ISBN: 978-3-540-45716-9
eBook Packages: Springer Book Archive