Abstract
In the current embedded processors for media applications, up to 30% of the total processor power is consumed in the instruction memory hierarchy. In this context, we present an inherently low energy clustered instruction memory hierarchy template. Small instruction memories are distributed over groups of functional units and the interconnects are localized in order to minimize energy consumption. Furthermore, we present a simple profile based algorithm to optimally synthesize the L0 clusters, for a given application. Using a few representative multimedia benchmarks we show that up to 45% of the L0 buffer energy can be reduced using our clustering approach.
This work is supported in part by MESA under the MEDEA+ program
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© 2002 Springer-Verlag Berlin Heidelberg
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Jayapala, M., Barat, F., de Beeck, P.O., Catthoor, F., Deconinck, G., Corporaal, H. (2002). A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_26
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DOI: https://doi.org/10.1007/3-540-45716-X_26
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