Abstract
This paper describes a slack budget distribution algorithm for ultralow power CMOS logic circuits in a VLSI design environment. We introduce Power-Aware Zero-Slack Algorithm (PA-ZSA), which distributes the surplus time slacks into the most power-hungry modules. The PA-ZSA ensures that the total slack budget is near-maximal and the total power is minimal as a poweraware version of the well-known zero-slack algorithm (ZSA). Based on these time slacks, we have conducted the low-power optimization at gate level by using technology scaling technique. The experimental results show that our strategy reduces average 36% of the total (static and dynamic) power over the conventional slack budget distribution algorithms.
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© 2002 Springer-Verlag Berlin Heidelberg
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Choi, Kw., Chatterjee, A. (2002). PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_18
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DOI: https://doi.org/10.1007/3-540-45716-X_18
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