Abstract
The aim of this paper is to present a new approach to creating high performance and low-power asynchronous circuits using high level design tools. In order to achieve this, we introduce a new timing model called Pseudo Delay-Insensitive model. To prove the goodness of this model, we present the results after comparing, for a set of benchmarks, our implementation with other implementations (synchronous and asynchronous).
This paper has been funded by Spanish Government Grant TIC 99/0474.
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© 2002 Springer-Verlag Berlin Heidelberg
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Garnica, O., Lanchares, J., Hermida, R. (2002). A New Methodology to Design Low-Power Asynchronous Circuits. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_12
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DOI: https://doi.org/10.1007/3-540-45716-X_12
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