Abstract
This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of bit-serial arithmetic circuits, which frequently appear in real-time DSP architectures. The potential of the proposed approach is examined through experimental synthesis of bitserial constant-coefficient multipliers. A new version of the EGG system can generate the optimal bit-serial multipliers of 8-bit coefficients with a 100% success rate in 15 minutes on an average.
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Motegi, M., Homma, N., Aoki, T., Higuchi, T. (2002). Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. In: Guervós, J.J.M., Adamidis, P., Beyer, HG., Schwefel, HP., Fernández-Villacañas, JL. (eds) Parallel Problem Solving from Nature — PPSN VII. PPSN 2002. Lecture Notes in Computer Science, vol 2439. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45712-7_80
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DOI: https://doi.org/10.1007/3-540-45712-7_80
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