A New DSP Architecture for Correcting Errors Using Viterbi Algorithm

Abstract

Due to the development of wireless internet and an increasing number of internet users, transferring and receiving errorless data in real-time can be the most important method to guarantee the QoS (Quality of Service) of internet. Convolutional encoding and Viterbi decoding are the widely used techniques to enhance the performance of BER (bit error rate) in the application area such as satellite communications systems. As a method to enhance the QoS of internet, a new DSP architecture that can effectively materialize the Viterbi algorithm, one of the algorithms that can correct errors during data transfer, is introduced in this paper. A new architecture and a new instruction set, which can handle the Viterbi algorithm faster, and simplify the Euclidean distance calculation, are defined. The performance assessment result shows that the proposed DSP can execute the Viterbi algorithm faster than other DSPs. Using 0.18 μm CMOS technology, the new DSP operates in 100 MHz, and consumes 218 μA/MHz.