Abstract
Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available on a single chip, the “on-chip multiprocessor” has been proposed as a promising alternative to processors based on the superscalar architecture. This paper examines the performance of vision benchmark tasks on an on-chip multiprocessor. To evaluate the performance, a program-driven simulator and its programming environment were developed. DARPA IU benchmarks were used for evaluation purposes. The benchmark includes integer, floating point, and extensive data movement operations. The simulation results show that the proposed on-chip multiprocessor can exploit thread-level parallelism effectively.
The work at USC was supported by the DARPA Data Intensive Systems program under contract F33615-99-1-1483 monitored by Wright Patterson Airforce Base.
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References
Prasanna Kumar, V.: Parallel Architectures and Algorithms for Image Understanding. Academic Press (1991)
Wang, C, Bhat, P., and Prasanna, V.: High Performance Computing for Vision. IEEE Proceedings, Vol. 84, No. 7 (1996) 931–946
Annaratone, M., et al.: The Warp Computer: Architecture, Implementation, and Performance. IEEE Tr. Computers, Vol. 36, No. 12 (1987) 1523–1538
Weems, C., Riseman, E., and Hanson, A.: Image Understanding Architecture: Exploiting Potential Parallelism in Machine Vision. IEEE Computer, Vol. 25, No. 2 (1992) 65–68
Wilson, J.: Challenges and Trends in Processor Design. IEEE Computer, Vol. 30, No. 1 (1997) 39–50
Wall, D.: Limits of Instruction Level Parallelism. WRL Research Report, Digital Western Research Laboratory (1993)
Hammond, L., et al.: A Single-Chip Multiprocessor. IEEE Computer, Vol. 30, No. 9 (1997) 79–85
Singh, J., Weber, W., and Gupta, A.: SPLASH: Stanford Parallel Applications for Shared Memory. Computer Architecture News, Vol. 20, No. 1 (1992) 5–44
Weems, C, et al.: The DARPA Image Understanding Benchmark for Parallel Computers. Journal of Parallel and Distributed Computing, Vol. 11, No. 1 (1991) 1–24
Park, K., et al.: On-Chip Multiprocessing with Simultaneous Multithreading. Technical Report, ETRI (1999)
POSIX P1003.4a: Threads Extension for Portable Operating Systems, IEEE (1994)
Burger, D. and Austin, T.: The SimpleScalar Tool Set, Version 2.0. Technical Report, University of Wisconsin (1997)
Bondalapati, K., Dutta, D., Narayanan, S., Prasanna, V. K., Ragahavendra, C, and Seshadri, A.: Optimizing DRAM-based Memory System Performance. Submitted to the 27th Annual International Symposium on Computer Architecture
Musmanno, J. F.: DARPA DIS Benchmarks. Atlantic Aerospace Electronics Corp. (1999)
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Chung, Y., Park, K., Hahn, W., Park, N., Prasanna, V.K. (2000). Performance of On-Chip Multiprocessors for Vision Tasks (Summary). In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_32
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DOI: https://doi.org/10.1007/3-540-45591-4_32
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