Abstract
This paper presents a new superscalar architecture for fast discrete cosine transform (DCT). Comparing with the general SIMD architecture, it speeds up the DCT computation by a factor of two at the cost of small additional hardware overheads.
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References
J. Hilgenstock, et al., “A video signal processor for MIMD multiprocessing”, Proceedings of Design Automation Conference, 1998, pp. 50–55.
R. B. Lee, “multimedia extensions for general-purpose processors”, IEEE Workshop on Signal Processing Systems, 1997, pp. 9–23
A. N. Netravali and B. G. Haskell, “Digital Pictures,-Representation, Compression, and Standards”, Plenum Press, 1995.
Zhang Yong, “Research on Video Encoder Design”, Ph. D. Dissertation, Zhejiang University, 1999.
D. A. Patterson, J. L. Hennessy, “Computer Architecture a Quantitative Approach”, Morgan Kaufmann Publishers Inc., 1996.
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© 2000 Springer-Verlag Berlin Heidelberg
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Yong, Z., Zhang, M. (2000). A Novel Superscalar Architecture for Fast DCT Implementation. In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_23
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DOI: https://doi.org/10.1007/3-540-45591-4_23
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Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-67442-9
Online ISBN: 978-3-540-45591-2
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