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MAJC-5200: A High Performance Microprocessor for Multimedia Computing

  • Subramania Sudharsanan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1800)

Abstract

The newly introduced Microprocessor Architecture for Java Computing (MAJC) supports parallelism in a hierarchy of levels: multiprocessors on chip, vertical micro threading, instruction level parallelism via a very long instruction word architecture (VLIW) and SIMD. The first implementation, MAJC-5200, includes some key features of MAJC to realize a high performance multimedia processor. Two CPUs running at 500 MHz are integrated into the chip to provide 6.16 GFLOPS and 12.33 GOPS with high speed interfaces providing a peak input-output (I/O) data rate of more than 4.8 G Bytes/second. The chip is suitable for a number of applications including graphics/multimedia processing for high-end set-top boxes, digital voice processing for telecomm unications, and advanced imaging.

Keywords

Data Cache Single Instruction Multiple Data Very Long Instruction Word Instruction Cache Instruction Level Parallelism 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architecture, Second Edition, Kluwer, Boston, 1997.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Subramania Sudharsanan
    • 1
  1. 1.Sun Microsystems, Inc.Palo AltoUSA

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