Abstract
In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed shift switching mechanism by letting the switch array automatically generate a semaphore to indicate the end of each domino process. This reduces the complexity of the architecture and improves the performance significantly.
The work was supported by National Science Foundation under grant MIP-9630870.
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References
I. S. Hwang, and A. L.. Fischer, Ultrafast compact 32-bit CMOS adders in multi-output domino logic, IEEE J. Solid-State Circ., 24, No 2 April 1989, pp. 358–369.
J. Jang, H. Park and V. K. Prasanna, A bit model of the reconfigurable mesh, Proc. of the Workshop on Reconfigurable Architectures, the 8th IPPS, Cancun, Maxico, 1994.
R._H. Krambeck, C. M. Lee, and H.S. Law, High-Speed Compact Circuits with CMOS, IEEE Journal of Solid-State Circuits, Vol SC-17, No. 3, June, 1982.
R. Lin, Shift switching and novel arithmetic schemes, in Proc. of 29th Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, CA, Nov. 1995.
R. Lin, A Reconfigurable Low-power High performance Matrix Multiplier Design, Proc. of 1th Intl. Symp. on Quality of Electronic Design, San Jose, California. March 2000.
R. Lin, Parallel VLSI Shift Switch Logic Devices, US Patent, Serial No. 09/022,248, 1999.
R. Lin and S. Olariu, Reconfigurable shift switching parallel comparators, in Intl. Journal of VLSI Design, March, 1999.
R. Lin and S. Olariu, Efficient VLSI architecture for Columnsort, IEEE Transactions on Very Large Scale Integration (VLSI) systems, VOL. 7, No. 1. March, 1999.
R. Lin, and S. Olariu, Reconfigurable buses with shift switching —concept and architectures, in IEEE Trans. on Parallel And Distributed System. January 1995.
R. Lin, K. Nakano, S. Olariu, M.C. Pintoti, J.L. Schwing, A.Y. Zomaya Scalable hardware-algorithms for binary prefix sums, in Proc. of 6th International Workshop on Reconfigurable Architecture(RAW), 1999.
R. Miller, V. K. P. Kumar, D. Reisis, and Q. F. Stout, Parallel Computations on Reconfigurable Meshes, IEEE Transactions on Computers, 42 (1993), 678–692.
N. Weste and K. Eshraghian, PRINCIPLES OF CMOS VLSI DESIGN, A systems Perspective (Second Edition), Addison-Wesley Publishing Company, 1993.
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Lin, R., Schwing, J.L. (2000). A Non-Binary Parallel Arithmetic Architecture. In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_19
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DOI: https://doi.org/10.1007/3-540-45591-4_19
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