A Non-Binary Parallel Arithmetic Architecture
In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed shift switching mechanism by letting the switch array automatically generate a semaphore to indicate the end of each domino process. This reduces the complexity of the architecture and improves the performance significantly.
KeywordsVery Large Scale Integration Reconfigurable Architecture Block Symbol Level Delay Inverter Delay
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