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A Non-Binary Parallel Arithmetic Architecture

  • Rong Lin
  • James L. Schwing
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1800)

Abstract

In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed shift switching mechanism by letting the switch array automatically generate a semaphore to indicate the end of each domino process. This reduces the complexity of the architecture and improves the performance significantly.

Keywords

Very Large Scale Integration Reconfigurable Architecture Block Symbol Level Delay Inverter Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Rong Lin
    • 1
  • James L. Schwing
    • 2
  1. 1.Department of Computer ScienceSUNY at GeneseoGeneseo
  2. 2.Department of Computer ScienceCentral Washington UniversityEllensburg

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