Abstract
A PRAM (Parallel Random Access Machine) [4] is the parallel computational model most notable for supporting the parallel algorithmic theory. It consists of a number of processors sharing a common memory. The processors communicate by exchanging data through a shared memory cell. Each processor can access any memory cell at one unit of time and all processors operate synchronously under the control of a common clock. These facts make the model a very advantageous platform for considering the inherent parallelism of problems. How ever, the development of parallel computers which fit this model has not quite matched the theoretical requests. The researches focusing on the reduction of this gap has been carried out [2, 5, 6, 7, 8, 9]. However, most of them give only theoretical analysis; the implementation of the PRAM on hardware level is seldom seen.
This work is supported by the Grant-in-Aid for Scientific Research (B)(2) 10205209 (1999) from the Ministry of Education, Science, Sports and Culture of Japan.
Corresponding e-mail address is: wada@elcom.nitech.ac.jp
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© 2000 Springer-Verlag Berlin Heidelberg
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Imai, M. et al. (2000). A Hardware Implementation of PRAM and its Performance Evaluation. In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_18
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DOI: https://doi.org/10.1007/3-540-45591-4_18
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