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A Hardware Implementation of PRAM and its Performance Evaluation

  • M. Imai
  • Y. Hayakawa
  • H. Kawanaka
  • W. Chen
  • K. Wada
  • C. D. Castanho
  • Y. Okajima
  • H. Okamoto
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1800)

Abstract

A PRAM (Parallel Random Access Machine) [4] is the parallel computational model most notable for supporting the parallel algorithmic theory. It consists of a number of processors sharing a common memory. The processors communicate by exchanging data through a shared memory cell. Each processor can access any memory cell at one unit of time and all processors operate synchronously under the control of a common clock. These facts make the model a very advantageous platform for considering the inherent parallelism of problems. How ever, the development of parallel computers which fit this model has not quite matched the theoretical requests. The researches focusing on the reduction of this gap has been carried out [2, 5, 6, 7, 8, 9]. However, most of them give only theoretical analysis; the implementation of the PRAM on hardware level is seldom seen.

Keywords

Memory Cell Shared Memory Memory Unit Access Request Processor Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • M. Imai
    • 1
  • Y. Hayakawa
    • 1
  • H. Kawanaka
    • 1
  • W. Chen
    • 1
  • K. Wada
    • 1
  • C. D. Castanho
    • 1
  • Y. Okajima
    • 1
  • H. Okamoto
    • 1
  1. 1.Nagoya Institute of TechnologyGokiso, Show a, NagayaJapan

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