One Flip per Clock Cycle
Stochastic Local Search (SLS) methods have proven to be successful for solving propositional satisfiability problems (SAT). In this paper, we show a hardware implementation of the greedy local search procedure GSAT. With the use of field programmable gate arrays (FPGAs), our implementation achieves one flip per clock cycle by exploiting maximal parallelism and at the same time avoiding excessive hardware cost. Experimental evaluation of our prototype design shows a speedup of two orders of magnitude over optimized software implementations and at least one order of magnitude over existing hardware schemes. As far as we are aware, this is the fastest known implementation of GSAT. We also introduce a high level algorithmic notation which is convenient for describing the implementation of such algorithms in hardware, as well as an appropriate performance measure for SLS implementations in hardware.
KeywordsClock Cycle Field Programmable Gate Array Satisfying Assignment FPGA Implementation Gate Delay
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