Abstract
When Image Processing Programs (IPP) are targeted to Instruction Level Parallel architectures that perform dynamic instruction scheduling, register allocation is the key action to expose the high parallelism degree typically present in the loops of such programs.
This paper presents two main contributions to the register allocation for IPP loop parallelization: i) a framework to identify the inefficiencies of the two basic approaches to register allocation — the first based on compiling techniques and the second based on hardware mechanisms for register renaming; ii) a novel technique that eliminates the inefficiencies of both approaches. Some experimental results show the effectiveness of this technique.
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Zingirian, N., Maresca, M. (2000). Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs. In: Bubak, M., Afsarmanesh, H., Hertzberger, B., Williams, R. (eds) High Performance Computing and Networking. HPCN-Europe 2000. Lecture Notes in Computer Science, vol 1823. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45492-6_34
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DOI: https://doi.org/10.1007/3-540-45492-6_34
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