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Integrated Provision of QoS Guarantees to Unicast and Multicast Traffic in Packet Switches

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2170))

Abstract

Multi-stage packet switches that feature a limited amount of buffers in the switching fabric and distribute most of their buffering capacity over the port cards have recently gained popularity due to their scalability properties and flexibility in supporting Quality-of- Service (QoS) guarantees. In such switches, the replication of multicast packets typically occurs at the outputs of the switching fabric. This approach minimizes the amount of resources needed to sustain the internal expansion in traffic volume due to multicasting, but also exposes multicast flows to head-of-line (HOL) blocking in the ingress port cards. Access regulation to the fabric buffers is of the utmost importance to safeguard the QoS of multicast flows against HOL blocking.

We add minimal overhead to a well-known distributed scheduler for multi-stage packet switches to define the Generalized Distributed Multilayered Scheduler (G-DMS), which achieves full support of QoS guarantees for both unicast and multicast flows. The novelty of the G-DMS is in the mechanism that regulates access to the fabric buffers, which combines selective backpressure with the capability of dropping copies of multicast packets that violate the negotiated profiles of the corresponding flows.

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References

  1. D. C. Stephens and H. Zhang, “Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture,” Proceedings of IEEE INFOCOM’ 98, March 1998.

    Google Scholar 

  2. D. C. Stephens, “Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture,” M.S. Thesis, Carnegie Mellon University, Pittsburgh, PA, May 1998.

    Google Scholar 

  3. F. M. Chiussi and A. Francini, “Providing QoS Guarantees in Packet Switches,” Proceedings of IEEE GLOBECOM’ 99, High-Speed Networks Symposium, Rio de Janeiro, Brazil, December 1999.

    Google Scholar 

  4. F. M. Chiussi and A. Francini, “A Distributed Scheduling Architecture for Scalable Packet Switches,” IEEE Journal on Selected Areas in Communications, Vol. 18, No. 12, pp. 2665–2683, December 2000.

    Article  Google Scholar 

  5. J. C. R. Bennett and H. Zhang, “Hierarchical Packet Fair Queueing Algorithms,” Proceedings of ACM SIGCOMM’ 96, pp. 143–156, August 1996.

    Google Scholar 

  6. F. M. Chiussi, J. G. Kneuer, and V. P. Kumar, “Low-Cost Scalable Switching Solutions for Broadband Networking: The ATLANTA Architecture and Chipset,” IEEE Communications Magazine, Vol. 35, No. 12, pp. 44–53, December 1997.

    Article  Google Scholar 

  7. U. Briem, E. Wallmeier, C. Beck, and F. Matthiesen, “Traffic Management for an ATM Switch with Per-VC Queueing: Concept and Implementation,” IEEE Communications Magazine, Vol. 36, No. 1, pp. 88–93, January 1998.

    Article  Google Scholar 

  8. F. M. Chiussi, Y. Xia, and V. P. Kumar, “Backpressure in Shared-Memory-Based ATM Switches under Multiplexed Bursty Sources,” Proceedings of IEEE INFOCOM’ 96, pp. 830–843, March 1996.

    Google Scholar 

  9. B. Prabhakar, N. McKeown, and R. Ahuja, “Multicast Scheduling for Input-Queued Switches,” IEEE Journal on Selected Areas in Communications, Vol. 15, No. 5, pp. 855–866, June 1997.

    Article  Google Scholar 

  10. N. McKeown,, “A Fast Switched Backplane for a Gigabit Switched Router,” Business Communications Review, Vol. 27, No. 12, December 1997.

    Google Scholar 

  11. ATM Forum Traffic Management Specification, Version 4.0, April 1996.

    Google Scholar 

  12. Y. Tamir and G. Frazier, “High Performance Multiqueue Buffers for VLSI Communication Switches,” Proceedings of 15th Annual Symposium on Computer Architectures, pp. 343–354, June 1988.

    Google Scholar 

  13. D. Stiliadis and A. Varma, “A General Methodology for Designing Efficient Traffic Scheduling and Shaping Algorithms,” Proceedings of IEEE INFOCOM’ 97, April 1997.

    Google Scholar 

  14. J. C. R. Bennett and H. Zhang, “WF2Q:Worst-case FairWeighted Fair Queueing,” Proceedings of IEEE INFOCOM’ 96, pp. 120–128, March 1996.

    Google Scholar 

  15. A. K. Parekh and R. G. Gallager, “A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single-Node Case,” IEEE/ACM Transactions on Networking, pp. 344–357, June 1993.

    Google Scholar 

  16. S. J. Golestani, “A Self-Clocked Fair Queueing Scheme for Broadband Applications,” Proceedings of IEEE INFOCOM’ 94, pp. 636–646, April 1994.

    Google Scholar 

  17. D. Stiliadis and A. Varma, “Latency-rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms,” Proceedings of IEEE INFOCOM’ 96, pp. 111–119, March 1996.

    Google Scholar 

  18. M. Katevenis, S. Sidiropoulos, and C. Courcoubetis, “Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip,” IEEE Journal on Selected Areas in Communications, vol. 9, pp. 1265–1279, October 1991.

    Article  Google Scholar 

  19. F. M. Chiussi and A. Francini, “Advances in Implementing Fair Queueing Schedulers in Broadband Networks,” Proceedings of IEEE ICC’ 99, June 1999 (Invited paper).

    Google Scholar 

  20. A. Francini, F. M. Chiussi, R. T. Clancy, K. D. Drucker, and N. E. Idirene, “Enhanced Weighted Round Robin Schedulers for Bandwidth Guarantees in Packet Networks,” Proceedings of QoS-IP 2001, pp. 205–221, Rome, Italy, January 2001.

    Google Scholar 

  21. F. M. Chiussi, A. Francini, D. A. Khotimsky, and S. Krishnan, “Feedback Control in a Distributed Scheduling Architecture,” Proceedings of IEEE GLOBECOM 2000, High-Speed Networks Symposium, San Francisco, CA, November 2000.

    Google Scholar 

  22. A. Francini and F. M. Chiussi, “Minimum-Latency Dual-Leaky-Bucket Shapers for Packet Multiplexers: Theory and Implementation,” Proceedings of IWQoS 2000, pp. 19–28, Pittsburgh, PA, June 2000.

    Google Scholar 

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© 2001 Springer-Verlag Berlin Heidelberg

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Francini, A., Chiussi, F.M. (2001). Integrated Provision of QoS Guarantees to Unicast and Multicast Traffic in Packet Switches. In: Palazzo, S. (eds) Evolutionary Trends of the Internet. IWDC 2001. Lecture Notes in Computer Science, vol 2170. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45400-4_24

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  • DOI: https://doi.org/10.1007/3-540-45400-4_24

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42592-2

  • Online ISBN: 978-3-540-45400-7

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