Abstract
In this communication adiabatic and conventional gates with a different fan-in are modeled and analytically compared. The comparison is carried out assuming both an assigned power supply and setting it to minimize power consumption. The analysis leads to simple expressions, which allow to understand how the power advantage of adiabatic logic changes by increasing the fan-in of the implemented gate. The analytical results were validated by means of Spice simulations using a 0.8 μm CMOS technology.
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Alioto, M., Palumbo, G. (2000). Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_28
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DOI: https://doi.org/10.1007/3-540-45373-3_28
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