Abstract
Coarse-grain reconfigurable architectures promise to be more adequate for computational tasks due to their better efficiency and higher speed. Since the coarse granularity implies also a reduction of flexibility, a universal architecture seems to be hardly feasible, especially under consideration of low power applications like mobile communication. Based on the KressArray architecture family, a design-space exploration system is being implemented, which supports the designer in finding an appropriate architecture featuring an optimized performance / power trade-off for a given application domain. By comparative analysis of the results of a number of different experimental application-to-array mappings, the explorer system derives architectural suggestions. This paper proposes the application of the exploration approach for low power KressArrays. Hereby, both the interconnect power dissipation and the operator activity is taken into account.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
J. Rabaey. “Low-Power Silicon Architectures forWireless Communications”; Embedded Tutorial, ASP-DAC 2000, Yokohama, Japan, Jan. 2000.
R. Hartenstein (invited paper): The Microprocessor is no more General Purpose:whyFuture Reconfigurable Platforms will win; Int’l Conf. on InnovativeSystemsin Silicon, ISIS’97, Austin,Texas,USA,Oct1997
E. Mirsky, A. DeHon: „MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, Proc. FPGAs for Custom Computing Machines, pp. 157–166, IEEE CS Press, Los Alamitos, CA, U.S.A., 1996.
A. Marshall et al.: A Reconfigurable Arithmetic Array for Multimedia Applications; FPGA’99, Int’l Symposium on Field Programmable Gate Arrays, Monterey, CA, U.S.A., Febr. 21-23, 1999
C. Ebeling, D. Cronquist, P. Franklin: „RaPiD: Reconfigurable Pipelined Datapath”, Int’lWorkshop on Field Programmable Logic and Applications, FPL’96, Darmstadt, Germany, Sept 1996.
R. A. Bittner, P. M. Athanas and M. D. Musgrove: „Colt: An Experiment in Wormhole Run-time Reconfiguration”; SPIE Photonics East `96, Boston, MA, USA, November 1996.
R. Kress et al.: A Datapath Synthesis System for the Reconfigurable Datapath Architecture; Asia and South Pacific Design Automation Conf. (ASP-DAC’95), Chiba, Japan, Aug. 29-Sept. 1, 1995
R. Kress: „A Fast Reconfigurable ALUs for Xputers”, Ph.D. thesis, Univ. Kaiserslautern, 1996.
E. Waingold et al.: „Baring it all to Software: Raw Machines”, IEEE Computer 30, pp. 86–93.
S. C. Goldstein, H. Schmit, et al.: „PipeRench: A Coprocessor for Streaming Multimedia Acceleration”; Int’l Symposium on Computer Architecture 1999, Atlanta, GA, USA, May 1999.
A. Abnous, K. Seno, Y. Ichikawa, M. Wan and J. Rabaey: Evaluation of a Low-Power Reconfigurable DSP-Architecture; Proceedings of the Reconfigurable Architectures Workshop, Orlando, Florida, USA, March 1998.
H. Zhang, M. Wan, V. George and J. Rabaey: Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs; Proceedings of the WVLSI, Orlando, Florida, USA, April 1999.
R. Hartenstein, M. Herz, Th. Hoffmann, U. Nageldinger: KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures; 5th Asia and South Pacific Design Automation Conference 2000, ASP-DAC 2000, Yokohama, Japan, January 25-28, 2000
L. Guerra, M. Potkonjak and J. Rabaey: „System-Level Design Guidance Using Algorithm Properties”; IEEE VLSI Signal Processing Workshop, 1994.
L. Kruse, E. Schmidt, G. Jochens, A. Stammermann andW. Nebel: Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints; Proceedings of the European Design and Test Conference DATE 2000.
L. Kruse, E. Schmidt, G. Jochens and W. Nebel: Lower and Upper Bounds on the Switching Activity in Scheduled Data Flow Graphs; Proceedings of ISPLED 1999.
W. Pedrycz: „Fuzzy Modelling-Paradigms and Practice”; Kluwer Academic Publishers, 1996.
B.R. Gaines: „Foundations of Fuzzy Reasoning”; Int’l Journal of Man-Machine Studies, Vol. 8, 1976.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Hartenstein, R., Hoffmann, T., Nageldinger, U. (2000). Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_12
Download citation
DOI: https://doi.org/10.1007/3-540-45373-3_12
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-41068-3
Online ISBN: 978-3-540-45373-4
eBook Packages: Springer Book Archive