ARPIA: A High-Level Evolutionary Test Signal Generator

  • Fulvio Corno
  • Gianluca Cumani
  • Matteo Sonza Reorda
  • Giovanni Squillero
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2037)


The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones.


Evolutionary Algorithm Clock Cycle Fault Model Fault Coverage Fault Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Fulvio Corno
  • Gianluca Cumani
  • Matteo Sonza Reorda
  • Giovanni Squillero
    • 1
  1. 1.Dipartimento di Automatica e InformaticaPolitecnico di TorinoTorinoItaly

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