Abstract
We investigate non blocking, variable length packet switches by focusing on performance evaluation and architectures to increase the throughput of such switches. With TCP/IP becoming the dominant protocol suite in the Internet, the analysis of variable length packet switches is necessary to understand the performance of the core routers and switches. We first present analytic models for delays and overflow probabilities in a variable length packet switch with finite buffers for both Poisson and self-similar packet arrival processes. The second part of the paper investigates various means to increase the throughput of these switches. As an alternative to VOQ-CIOQ switches that are known to be necessary to provide practical 100% throughput and QoS we consider a FIFO-CIOQ switch with speedup and multiple parallel planes of switches to minimise the delay in the input queue. We present analytic models for evaluating the impact of speedup and parallelism on increasing the throughput of the switch and show that with a parallelism of 4, it is possible to achieve 99.9% throughput.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
A. T. Andersen and B. F. Nielsen, “A Markovian approach for modeling packet traffic with long-range dependence,” IEEE Jour on Sel Areas in Commun, vol. 16, no. 5, pp. 719–732, June 1998.
A. Baiocchi and N. Bléfari-Melazzi, “Steady-State Analysis of the MMPP/G/1/K Queue,” IEEE Trans on Commun, vol. 41, no. 4, pp. 531–534, Apr 1993.
A. Baiocchi and N. Bléfari-Melazzi, “Analysis of the Loss Probability of the MAP/G/1/K Queue Part II: Approximations and Numerical Results,” Stochastic Models, vol. 10, no. 4, pp. 895–925, 1994.
J.G. Dai and Balaji Prabhakar, “The Throughput of Data Switches with and without Speedup,” Proc of IEEE Infocom-2000, Mar 2000.
A. Erramilli, O. Narayan and W. Wilinger, “Experimental Queuing Analysis with LRD Packet Traffic,” IEEE/ACM Trans on Networking, vol 4, no 2, Apr 1996.
W. Fischer and K. Meier-Hellstern, “The Markov-modulated Poisson process (MMPP) cookbook,” Performance Evaluation, vol. 18, no. 2, pp. 149–171, 1993.
S. W. Fuhrman, “Performance of a Packet Switch with a Crossbar Architecture,” IEEE Trans. on Commun., vol COM-41, pp. 486–491, 1993.
E. Glenbe and G. Pujolle, “Introduction to Queueing Networks,” John Wiley and Sons, 1987.
M. J. Karol, M. G. Hluchyj and S. P. Morgan, “Input Versus Output Queuing on a Space-Division Packet Switch,” IEEE Trans on Commun, vol. COM-35, no. 12, pp. 1347–1356, Dec 1987.
W. E. Leland, M. S. Taqqu, W. Willinger and D. V. Wilson, “On the self-similar nature of Ethernet traffic (Extended Version),” IEEE/ACM Transactions on Networking, vol. 2, no. 1, pp. 1–15, Feb 1994.
D. Manjunath and B. Sikdar, “Input Queued Packet Switches for Variable Length Packets: A Continuous Time Analysis,” Proc of IEEE Broadband Switching Systems, Kingston, ON, pp. 65–69, June 1999.
D. Manjunath and B. Sikdar, “Variable Length Packet Switches: Delay Analysis of Crossbar Switching under Poisson and Self Similar Traffic,” Proc of IEEE Infocom-2000, Tel Aviv, Israel, Mar 2000.
N. McKeown, V. Anantharam and J. Walrand, “Achieving 100% throughput in an Input Queued Switch,” Proc of IEEE Infocom-96, pp.296–302.
N. McKeown and A. Mekkittikul, “A Starvation Free Algorithm for Achieving 100% Throughput in an Input Queued Switch”, Proc of ICCCN 96, Oct.1996.
N. McKeown and A. Mekkittikul, “A Practical Scheduling Algorithm to Achieve 100% Throughput in Input-Queued Switches”, Proc of IEEE INFOCOM-98, Apr.1998.
N. McKeown, “iSLIP: A Scheduling Algorithm for Input Queued Switches,” IEEE/ACM Trans on Networking, vol 7, pp 188–201, 1999.
Y. Oie, M. Murata, K. Kubota and H. Miyahara, “Effiect of Speedup in Nonblocking Packet Switch,” Proc of IEEE ICC, 1989, pp 410–414.
H. Perros, “Queuing Networks with Blocking,” Oxford University Press, 1994.
K. Yoshigoe and K. Christensen, “A Parallel Polled Virtual Output Queued Switch with a Buffered Crossbar,” Proc of IEEE HPSR, pp. 271–275, May 2001.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Manjunath, D., Sikdar, B. (2001). Variable Length Packet Switches: Input Queued Fabrics with Finite Buffers, Speedup, and Parallelism. In: Monien, B., Prasanna, V.K., Vajapeyam, S. (eds) High Performance Computing — HiPC 2001. HiPC 2001. Lecture Notes in Computer Science, vol 2228. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45307-5_33
Download citation
DOI: https://doi.org/10.1007/3-540-45307-5_33
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-43009-4
Online ISBN: 978-3-540-45307-9
eBook Packages: Springer Book Archive