Putting Data Value Predictors to Work in Fine-Grain Parallel Processors

Abstract

Recent work has shown that the hurdles imposed by data dependences on parallelism can be overcome to some extent with the use of data value prediction. This paper highlights how data value history is affected when implementing data value predictors in fine-grained parallel processors, wherein microarchitectural issues affect the recorded history. Simulation studies show that mispredictions increase and correct predictions decrease when the recorded history is not updated properly. The paper also investigates techniques for overcoming the effects of value history disruption. The investigated techniques rely on extrapolation of outdated history so as to make it up-to-date, and utilization of misprediction information to turn off predictions of subsequent instances of the mispredicted instruction. We evaluate the proposed techniques using a cycle-accurate simulator for a superscalar processor. Results from this study indicate that the extrapolation technique is indeed able to provide up-to-date history in most of the cases, and is able to recoup most of the ground lost due to microarchitectural effects. Utilization of misprediction information helps to further reduce the number of mispredictions, although in some cases it reduces the number of correct predictions also.