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Towards Energy-Aware Iteration Space Tiling

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Languages, Compilers, and Tools for Embedded Systems (LCTES 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1985))

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Abstract

Iteration space (loop) tiling is a widely used loop-level compiler optimization that can improve performance of array-dominated codes. But, in current designs (in particular in embedded and mobile devices), low energy consumption is becoming as important as performance. Towards understanding the influence of tiling on system energy, in this paper, we investigate energy behavior of tiling.

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References

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Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802-6106

    M. Kandemir, N. Vijaykrishnan, M. J. Irwin & H. S. Kim

Authors
  1. M. Kandemir
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  2. N. Vijaykrishnan
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  3. M. J. Irwin
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  4. H. S. Kim
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Editor information

Editors and Affiliations

  1. Department of Computer Science, University of Virginia, School of Engineering and Applied Science, 22903-2442, VA, Charlottesville, USA

    Jack Davidson

  2. Department of Computer Engineering, Seoul National University, 151-742, Seoul, Korea

    Sang Lyul Min

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© 2001 Springer-Verlag Berlin Heidelberg

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Kandemir, M., Vijaykrishnan, N., Irwin, M.J., Kim, H.S. (2001). Towards Energy-Aware Iteration Space Tiling. In: Davidson, J., Min, S.L. (eds) Languages, Compilers, and Tools for Embedded Systems. LCTES 2000. Lecture Notes in Computer Science, vol 1985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45245-1_16

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  • DOI: https://doi.org/10.1007/3-540-45245-1_16

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41781-1

  • Online ISBN: 978-3-540-45245-4

  • eBook Packages: Springer Book Archive

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