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Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors

  • R. Govindarajan
  • Chihong Zhang
  • Guang R. Gao
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1863)

Abstract

Modern superscalar architectures with dynamic scheduling and register renaming capabilities have introduced subtle but important changes into the tradeoffs between compile-time register allocation and instruction scheduling. In particular, it is perhaps not wise to increase the degree of parallelism of the static instruction schedule at the expense of excessive register pressure which may result in additional spill code. To the contrary, it may even be beneficial to reduce the register pressure at the expense of constraining the degree of parallelism of the static instruction schedule. This leads to the following interesting problem: given a data dependence graph (DDG) G, can we derive a schedule S for G that uses the least number of registers ?

In this paper, we present a heuristic approach to compute the near-optimal number of registers required for a DDG G (under all possible legal schedules). We propose an extended list-scheduling algorithm which uses the above number of required registers as a guide to derive a schedule for G that uses as few registers as possible. Based on such an algorithm, an integrated approach for register allocation and instruction scheduling for modern superscalar architectures can be developed.

Keywords

List Schedule Minimum Register Register Allocation Instruction Schedule List Scheduler 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • R. Govindarajan
    • 1
  • Chihong Zhang
    • 2
  • Guang R. Gao
    • 2
  1. 1.Supercomputer Edn. & Res. Centre Dept. of Computer Science & AutomationIndian Institute of ScienceBangaloreIndia
  2. 2.Dept. of Electrical & Computer Engg.University of DelawareNewarkUSA

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