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Comprehensive Redundant Load Elimination for the IA-64 Architecture

  • Youngfeng Wu
  • Yong-fong Lee
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1863)

Abstract

For IA-64 architecture, a compiler can aggressively utilize control and data speculation to increase instruction-level parallelism. Aggressive speculation normally generates many speculative (control-speculative) and advanced (data-speculative) loads with the same addresses. Traditional redundant load elimination handles only regular loads. It cannot be straightforwardly applied to removing speculative and advanced loads. In this paper, we present a framework for comprehensive redundant load elimination, which correctly handles all six types of the following loads: regular loads, advanced loads, check loads, check advanced loads, speculative loads, and speculative advanced loads. Our preliminary experimental results demonstrate that it is important to perform comprehensive redundant load elimination in a compiler for architectures supporting control and data speculation.

Keywords

Critical Path Program Transformation Speculative Load Destination Register Program Point 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    D. M. Gallagher, W. Y. Chen, S. A. Mahlke, J. C. Gyllenhaal, W. W. Hwu, “Dynamic Memory Disambiguation Using the Memory Conflict Buffer,” Proceedings of the 6th International Conference on Architecture Support for Programming Languages and Operating Systems, San Jose, California, October 1994, pp. 183–195.Google Scholar
  2. 2.
    A. V. Aho, R. Sethi, J. D. Ullman, Compilers, Principles, Techniques, and Tools, Addison Wesley, 1987.Google Scholar
  3. 3.
    S. A. Mahlke, W. Y. Chen, R. A. Bringmann, R. E. Hank, W. W. Hwu, B. R. Rau, and M. S. Schlansker, “Sentinel Scheduling: A Model for Compiler-Controlled Speculative Execution,” Transactions on Computer Systems, Vol. 11, No. 4, Nov. 1993.Google Scholar
  4. 4.
    Intel Corp, “IA-64 Application Developers Architecture Guide,” May 1999.Google Scholar
  5. 5.
    Youfeng Wu and Yong-fong Lee, “Generalized Redundant Load Elimination for Architectures Supporting Control and Data Speculation,” Intel Microcomputer Research Labs Technical Report TR MRL 1997 23.0, October 1997.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Youngfeng Wu
    • 1
  • Yong-fong Lee
    • 1
  1. 1.Intel CorporationSanta Clara

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