The Scc Compiler: SWARing at MMX and 3D Now!

  • Randall J. Fisher
  • Henry G. Dietz
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1863)


Last year, we discussed the issues surrounding the development of languages and compilers for a general, portable, high-level SIMD Within A Register (SWAR) execution model. In a first effort to provide such a language and a framework for further research on this form of parallel processing, we proposed the vector-based language SWARC, and an experimental module compiler for this language, called Scc, which targeted IA32+MMX-based architectures.

Since that time, we have worked to expand the types of targets that Scc supports and to include optimizations based on both vector processing and enhanced hardware support for SWAR. This paper provides a more formal description of the SWARC language, describes the organization of the current version of the Scc compiler, and discusses the implementation of optimizations within this framework.


Intermediate Representation Strip Mining Expression Tree Target Architecture Vector Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Randall J. Fisher
    • 1
  • Henry G. Dietz
    • 1
  1. 1.School of Electrical and Computer EngineeringPurdue UniversityWest Lafayette

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