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A Compiler Framework for Tiling Imperfectly-Nested Loops

  • Yonghong Song
  • Zhiyuan Li
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1863)

Abstract

This paper presents an integrated compiler framework for tiling a class of nontrivial imperfectly-nested loops such that cache locality is improved. We develop a new memory cost model to analyze data reuse in terms of both the cache and the TLB, based on which we compute the tile size with or without array duplication. We determine whether to duplicate arrays for tiling by comparing the respective exploited reuse factors. The preliminary results with several benchmark programs show that the transformed programs achieve a speedup of 1.09 to 3.82 over the original programs.

Keywords

Cache Size Tile Size Program Language Design Innermost Loop Tiling Scheme 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Yonghong Song
    • 1
  • Zhiyuan Li
    • 1
  1. 1.Department of Computer SciencesPurdue UniversityWest Lafayette

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