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The Design and Verification of a Sorter Core

  • Koen Claessen
  • Mary Sheeran
  • Satnam Singh
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2144)

Abstract

We show how the Lava system is used to design and analyse fast sorting circuits for implementation on Field Programmable Gate Arrays (FPGAs). We present both recursive and periodic sorting networks, based on recursive merging networks such as Batcher’s bitonic and odd-even mergers. We show how a design style that concentrates on capturing connection patterns gives elegant generic circuit descriptions. This style aids circuit analysis and also gives the user fine control of the final layout on the FPGA. We demonstrate this by analysing andd implementing four sorters on a Xilinx Virtex-II™ FPGA. Performance figures are presented.

Keywords

Field Programmable Gate Array Connection Pattern Input List Sorting Network Wiring Pattern 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Koen Claessen
    • 1
  • Mary Sheeran
    • 1
  • Satnam Singh
    • 2
  1. 1.Chalmers University of TechnologyUSA
  2. 2.Xilinx, Inc.USA

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