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Verification of Basic Block Schedules Using RTL Transformations

  • Rajesh Radhakrishnan
  • Elena Teica
  • Ranga Vemuri
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2144)

Abstract

We present an approach to aid in debugging/development of scheduling algorithm implementations. Our technique makes use of a sequence of a correctness-preserving RTL transformation called Register Transfer Split (RTS), to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.

Keywords

Schedule Algorithm Discrete Cosine Transform Data Path Register Transfer High Level Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Rajesh Radhakrishnan
    • 1
  • Elena Teica
    • 1
  • Ranga Vemuri
    • 1
  1. 1.ECECS DepartmentUniversity of CincinnatiCincinnati

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