Abstract
It is explained how Dill (Digital Logic in Lotos) can specify and analyse hardware timing characteristics using ET-Lotos (Enhanced Timed Lotos — the ISO Language Of Temporal Ordering Specification). Hardware functionality and timing characteristics are rigorously specified and then validated.
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© 2001 Springer-Verlag Berlin Heidelberg
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He, J., Turner, K.J. (2001). Specifying Hardware Timing with ET-Lotos . In: Margaria, T., Melham, T. (eds) Correct Hardware Design and Verification Methods. CHARME 2001. Lecture Notes in Computer Science, vol 2144. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44798-9_14
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DOI: https://doi.org/10.1007/3-540-44798-9_14
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