Specifying Hardware Timing with ET-Lotos

  • Ji He
  • Kenneth J. Turner
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2144)


It is explained how Dill (Digital Logic in Lotos) can specify and analyse hardware timing characteristics using ET-Lotos (Enhanced Timed Lotos — the ISO Language Of Temporal Ordering Specification). Hardware functionality and timing characteristics are rigorously specified and then validated.


Setup Time General Delay Digital Logic Input Change Operator Delta 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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    Ji He and Kenneth J. Turner. Dill (Digital Logic in Lotos) project web page., November 2000.
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    Luc Léonard and Guy Leduc. An enhanced version of timed Lotos and its application to a case study. In Richard L. Tenney, Paul D. Amer, and M. Ümit Uyar, editors, Proc. Formal Description Techniques VI, pages 483–500. North-Holland, Amsterdam, Netherlands, 1994.Google Scholar
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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Ji He
    • 1
  • Kenneth J. Turner
    • 1
  1. 1.Computing Science and MathematicsUniversity of StirlingStirlingScotland

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