Abstract
For data intensive applications like Digital Signal Processing, Image Processing, and Pattern Recognition, memory reads and writes constitute a large portion of the total design execution time. With the advent of on-chip memories, a rich hierarchy of physical memories is now available on a Reconfigurable Computer (RC). An intelligent usage of these memories can lead to a significant improvement in the latency of the overall design. This paper presents an automated heuristic-based memory mapping framework for RCs. We use a Tabu search guided heuristic, Rectangle Carving, to map a single data structure onto several instances of a memory type on the RC. We also introduce control logic to resolve potential memory access conflicts and to make the details of memory mapping transparent to the accessing logic.
This work is supported in part by the US Air Force, Wright Laboratory, WPAFB, under contract number F33615-97-C-1043.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Xilinx Corporation. “Using Virtex BlockRAMs”, 1999.
Altera Corporation. “FLEX 10K Embedded Programmable Logic Family Data Sheet”, May 2000.
Altera Corporation. “APEX 20K Programmable Logic Device Family Data Sheet”, March 2000.
P. Jha and N. Dutt. “High-Level Library Mapping for Memories”. In ACM Transactions on Design Automation of Electronic Systems, pages 566–603. ACM Press, July 2000.
M. Balakrishnan. “Allocation of Multiport Memories in Data Path Synthesis”. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 7, pages 536–540, April 1998.
I. Ahmad and C. Y. Chen. “Post-Process for Data Path Synthesis”. In Proceedings of International Conference on Computer Aided Design, pages 276–279. ACM Press, 1991.
D. Karchmer and J. Rose. “Definition and Solution of the Memory Packing Problem for Field-Programmable Systems”. In Proceedings of International Conference on Computer Aided Design, pages 20–26. ACM Press, November 1994.
S. Wilton. “Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memory”. PhD thesis, University of Toronto, 1997.
W. Ho and S. Wilton. “Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays”. In International Workshop on Field Programmable Logic and Applications, pages 111–123, September 1999.
I. Ouaiss and R. Vemuri. “Hierarchical Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers”. In Design Automation and Testing Conference of Europe, pages 284–293, Berlin, Germany, September 2000. Springer-Verlag.
I. Ouaiss and R. Vemuri. “Global Memory Mapping During Synthesis in FPGA-Based Reconfigurable Computers”. In Reconfigurable Architectures Workshop, pages 284–293, San Francisco, September 2000. Springer-Verlag.
F. Glover and M. Laguna. “Tabu Search”. Kluwer Academic Publishers, 1997.
I. Ouaiss and R. Vemuri. “Resource Arbitration in Reconfigurable Computing Environments”. In Proceedings of Design Automation and Test in Europe, pages 560–566. IEEE Computer Society Press, April 2000.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kasat, A., Ouaiss, I., Vemuri, R. (2001). Memory Synthesis for FPGA-Based Reconfigurable Computers. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_8
Download citation
DOI: https://doi.org/10.1007/3-540-44687-7_8
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42499-4
Online ISBN: 978-3-540-44687-3
eBook Packages: Springer Book Archive