Abstract
This paper discusses the suitability of reconfigurable computing architectures to different network routing methods. As an example of the speedup offered by reconfigurable logic, the implementation of Dijkstra’s shortest path routing algorithm is presented and its performance is compared to a microprocessor-based solution.
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© 2001 Springer-Verlag Berlin Heidelberg
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Tommiska, M., Skyttä, J. (2001). Dijkstra’s Shortest Path Routing Algorithm in Reconfigurable Hardware. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_73
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DOI: https://doi.org/10.1007/3-540-44687-7_73
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Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42499-4
Online ISBN: 978-3-540-44687-3
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