Skip to main content
SpringerLink
Log in

FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding

  • Conference paper
  • First Online:
Field-Programmable Logic and Applications (FPL 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2147))

Included in the following conference series:

Abstract

This paper presents a hardware implementation of an adaptive modelling unit for parallel binary arithmetic coding. The presented model combines the advantages of binary arithmetic coding where the coding process is simplified, with the benefits of multi-alphabet arithmetic coding where any type of data can be compressed. The modelling unit adopts a simple method to store and modify the information, making it able to process 8 bits per clock cycle and to increase substantially the arithmetic coding speed. This model has been implemented in an A500K130 ProASIC FPGA and offers a throughput of 256 Mbits/s.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. Nelson: The Data Compression Book, Prentice Hall (1991)

    Google Scholar 

  2. I.H. Witten et al: Arithmetic Coding for Data Compression, Communications of the ACM, Vol. 30, No. 6, (1987), pp. 520–540

    Article  Google Scholar 

  3. J. Jiang.: Novel Design of Arithmetic Coding for Data Compression, IEE Proceedings Computers and Digital Techniques, Vol. 142, No. 6, (1995),pp. 419–424

    Article  Google Scholar 

  4. K. M. Marks: A JBIG-ABIC Compression Engine for Digital Document Processing, IBM Journal of Research and Development, Vol. 42, No. 6, (1998), pp. 753–758

    Article  Google Scholar 

  5. S. Kuang, J. Jou, Y. Chen: The Design of an Adaptive On-Line Binary Arithmetic Coding Chip, IEEE TCAS-I, Vol. 45, No. 7, (1998), pp. 693–706

    Google Scholar 

  6. S. Mahapatra, J. L. Núñez, C. Feregrino-Uribe and S. Jones: Parallel Implementation of a Multialphabet Arithmetic Coding Algorithm, IEE Colloquium on Data Compression: Methods and Implementations, IEE Savoy Place, London, (1999)

    Google Scholar 

  7. A. Moffat: Linear Time Adaptive Arithmetic Coding, IEEE Transaction on Information Theory, Vol. 36, No. 2, (1990), pp. 401–406

    Article  MATH  MathSciNet  Google Scholar 

  8. R. Arnold, T. Bell: A Corpus for the Evaluation of Lossless Compression Algorithms, Data Compression Conference,(1997), pp. 201–210

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Electronic and Electrical Engineering Department, Institut für Grundlagen der Elektrotechnik und Elektronik (IEE) TU Dresden, 01062, Dresden, Germany

    Riad Stefo

  2. Electronic Systems Design Group, Loughborough University, Loughborough, Leics., LE11 3TU, UK

    José Luis Núñez, Claudia Feregrino & Simon Jones

  3. Dept. of Computer Science Engineering & Applications, Regional Engineering College, Rourkela -769 008, Orissa, India

    Sudipta Mahapatra

Authors
  1. Riad Stefo
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. José Luis Núñez
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Claudia Feregrino
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Sudipta Mahapatra
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Simon Jones
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Division of Informatics, University of Edinburgh, James Clerk Maxwell Building Mayfield Road, EH9 3JZ, Edinburgh, UK

    Gordon Brebner

  2. School of Electrical and Electronic Engineering, Queen’s University of Belfast, Ashby Building Stranmillis Road, BT9 5AH, Belfast, UK

    Roger Woods

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Stefo, R., Núñez, J.L., Feregrino, C., Mahapatra, S., Jones, S. (2001). FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_71

Download citation

  • DOI: https://doi.org/10.1007/3-540-44687-7_71

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42499-4

  • Online ISBN: 978-3-540-44687-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation