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Arithmetic Operation Oriented Reconfigurable Chip: RHW

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Field-Programmable Logic and Applications (FPL 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2147))

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Abstract

We have developed an ALU based reconfigurable device called RHW (Reconfigurable HardWare) that is designed to work with the CPU to accelerate the computation-intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. It is also important to develop high performance operation unit library to utilize function cells of RHW efficiently. This paper describes the basic architecture of the RHW, high performance operation unit library and evaluation results.

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References

  1. Yamauchi, T., et al.,’ Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW’, IEEE Workshop on FPGAs for Custom Computing Machines (FCCM’00), pp. 281–282, April (2000)

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  2. Wakabayashi, K. and Tanaka, H.,’ Global Scheduling Independent of Control Dependencies Based on Condition Vectors’, 29th DAC, pp. 112–115 (1992)

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  3. Yamauchi, T., et al.,’ SOP: A Reconfigurable Massively Parallel System and Its Control-Data-Flow based Compiling Method’, IEEE Workshop on FPGAs for Custom Computing Machines (FCCM-96), pp. 148–156, April (1996)

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  4. Goldstein, S.C., et al.,’ PipeRench: A Reconfigurable Architecture and Compiler’, Computer, April, pp. 70–77 (2000)

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© 2001 Springer-Verlag Berlin Heidelberg

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Yamauchi, T., Nakaya, S., Inuo, T., Kajihara, N. (2001). Arithmetic Operation Oriented Reconfigurable Chip: RHW. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_66

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  • DOI: https://doi.org/10.1007/3-540-44687-7_66

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42499-4

  • Online ISBN: 978-3-540-44687-3

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