Macrocell Architectures for Product Term Embedded Memory Arrays
We examine ways to increase product term usage efficiency and propose several new sharing architectures that addresses this problem. We also present a technology mapping algorithm for product term based FPGA embedded memory arrays. Our algorithm, pMapster, is used to investigate the effects of macrocell granularity and macrocell sharing on the amount of logic that can be packed into a product term embedded memory array.
KeywordsProgrammable Logic Product Term Technology Mapping Memory Array Seed Node
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