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Macrocell Architectures for Product Term Embedded Memory Arrays

  • Ernie Lin
  • Steven J. E. Wilton
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

We examine ways to increase product term usage efficiency and propose several new sharing architectures that addresses this problem. We also present a technology mapping algorithm for product term based FPGA embedded memory arrays. Our algorithm, pMapster, is used to investigate the effects of macrocell granularity and macrocell sharing on the amount of logic that can be packed into a product term embedded memory array.

Keywords

Programmable Logic Product Term Technology Mapping Memory Array Seed Node 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Ernie Lin
    • 1
  • Steven J. E. Wilton
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of British ColumbiaVancouverCanada

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