Abstract
This paper presents new achievements on the automatic mapping of abstract algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled with one or more memories. The compilation flow exposes operation- and functional-level parallelism, and speculative execution. Such expositions are efficiently represented in a hierarchical model. In order to take full advantage of such representation, the scheduling scope is significantly improved by merging basic blocks at loop boundaries and by considering the parallel execution of exposed concurrent loops. The paper describes the scheduling technique, shows a study on the impact of the merge operation, and reveals the improvements achieved when the exposed parallelism is fully satisfied.
Research partially supported by the Portuguese PRAXIS XXI Program under the scope of the AXEL Project PRAXIS/2/2.1/TIT/1643/95.
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Cardoso, J.M.P., Neto, H.C. (2001). Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_54
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DOI: https://doi.org/10.1007/3-540-44687-7_54
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