fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits

  • Parivallal Kannan
  • Shankar Balachandran
  • Dinesh Bhatia
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


Interconnection planning is becoming an important design issue for large FPGA based designs and ASICs. One of the most important issues for planning interconnection is the ability to predict the routability of a given design. In this paper, we introduce a new methodology, fGREP, for ultra-fast estimation of routing demands for placed circuits on FPGAs. Our method uses logic block fanout as a measure of available routing alternatives for routing a net. Experimental results on a large set of benchmark examples show that our predictions closely match with the detailed routing results of a well known router, namely VPR[1]. fGREP is simultaneously able to predict the peak routing demand (channel width) and the routing demands for every routing channel. It is currently used for postplacement estimation of routing demands, but can be used during the placement process also. fGREP can be used with any standard FPGA place and route flow.


Channel Width Field Programmable Gate Array Root Vertex Track Width FPGA Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    Vaughn Betz and Jonathan Rose, “VPR: A New Packing, Placement and Routing Tool for FPGA research,” in Field-Programmable Logic and Applications. Sep 1997, pp. 213–222, Springer-Verlag, Berlin.Google Scholar
  2. [2]
    H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, Reading, MA, 1990.Google Scholar
  3. [3]
    H. Van Marck, D. Stroobandt, and J. Van Campenhout, “Toward an Extension of Rent’s Rule for Describing Local Variations in Interconnection Complexity,” in Proceedings of the 4th International Conference for Young Computer Scientists, 1995, pp. 136–141.Google Scholar
  4. [4]
    G. Parthasarathy, M. Marek-Sadaowska, and A. Mukherjee, “Interconnect Complexity-aware FPGA Placement Using Rent’s Rule,” in To appear in, Proc. Intl. Workshop on System Level Interconnect Prediction (SLIP), April 2001.Google Scholar
  5. [5]
    Wei Li, “Routability Prediction for Hierarchical FPGAs,” in Proc. Great Lakes Symposium on VLSI, 1999.Google Scholar
  6. [6]
    Abbas A. El Gamal, “Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits,” IEEE Trans. CAS., Feb 1981.Google Scholar
  7. [7]
    S. Brown, J. Rose, and Z.G. Vranesic, “A Stochastic Model to Predict the Routability of Field Programmable Gate Arrays,” IEEE Transactions on CAD, pp. 1827–1838, Dec 1993.Google Scholar
  8. [8]
    R.G. Wood and R.A. Rutenbar, “FPGA Routing and Routability Estimation via Boolean Satisfiability,” in ACM International Symposium on FPGAs FPGA98. June 1998, ACM.Google Scholar
  9. [9]
    M. Wang and M. Sarrafzadeh, “Congestion Minimization During Placement,” in Proceedings of the 1999 International Symposium on Physical Design (ISPD), 1999.Google Scholar
  10. [10]
    Sudip K. Nag and R.A. Rutenbar, “Performance-driven Simultaneous Placement and Routing for FPGAs,” IEEE Transactions on CAD, June 1998.Google Scholar
  11. [11]
    S. Sastry and A.C. Parker, “Stochastic Models for Wireability Analysis of Gate Arrays,” IEEE Trans. on CAD, Jan 1986.Google Scholar
  12. [12]
    Larry McMurchie and Carl Ebeling, “PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs,” in ACM Symp. on FPGAs, FPGA95. ACM, 1995, pp. 111–117.Google Scholar
  13. [13]
    S. Brown, J. Rose, and Z.G. Vranesic, “A Detailed Router for Field Programmable Gate Arrays,” IEEE Transactions on CAD, May 1992.Google Scholar
  14. [14]
    G. Lemieux and S. Brown, “A Detailed Router for Allocating Wire Segments in FPGAs,” in ACM Physical Design Workshop, April 1993, pp. 215–226.Google Scholar
  15. [15]
    Parivallal Kannan, Shankar Balachandran, and Dinesh Bhatia, “fGREP Results for ISCAS-89 Benchmarks,” Tech. Rep., CICS, University of Texas at Dallas, 2001,

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Parivallal Kannan
    • 1
  • Shankar Balachandran
    • 1
  • Dinesh Bhatia
    • 1
  1. 1.Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer ScienceUniversity of Texas at DallasRichardsonUSA

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