Reconfigurable Breakpoints for Co-debug
Over the last decade, a large effort has gone into researching the use of FPGA devices for co-processing. Much of the emphasis of this work has been in the area of design entry tools. As FPGA co-processing moves into the mainstream, tools to support the complete design and implementation process are being more actively investigated. In particular, the ability to perform integrated hardware / software co-debug in these environments is of interest. One key element of FPGA co-processing is system synchronization and clock control. Today, some commercially available FPGA co-processing systems contain simple clock control such as single- and multi-stepping. Others have no clock control whatsoever, offering only a free-running system clock. In this paper a set of Reconfigurable Hardware Breakpoint cores is described. These cores are used to provide the control necessary for co-debug in FPGA co-processing systems and can be used to trace the flow of a circuit at run-time or control its operation. Reconfigurable hardware breakpoint cores are independent of circuit board clock implementation and are shipped as part of the Jbits™ Software Development Kit as Run-Time Parameterizable (RTP) Cores.
KeywordsClock Cycle Application Program Interface System Clock FPGA Device FPGA Design
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