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Reconfigurable Breakpoints for Co-debug

  • Tim Price
  • Cameron Patterson
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

Over the last decade, a large effort has gone into researching the use of FPGA devices for co-processing. Much of the emphasis of this work has been in the area of design entry tools. As FPGA co-processing moves into the mainstream, tools to support the complete design and implementation process are being more actively investigated. In particular, the ability to perform integrated hardware / software co-debug in these environments is of interest. One key element of FPGA co-processing is system synchronization and clock control. Today, some commercially available FPGA co-processing systems contain simple clock control such as single- and multi-stepping. Others have no clock control whatsoever, offering only a free-running system clock. In this paper a set of Reconfigurable Hardware Breakpoint cores is described. These cores are used to provide the control necessary for co-debug in FPGA co-processing systems and can be used to trace the flow of a circuit at run-time or control its operation. Reconfigurable hardware breakpoint cores are independent of circuit board clock implementation and are shipped as part of the Jbits™ Software Development Kit as Run-Time Parameterizable (RTP) Cores.

Keywords

Clock Cycle Application Program Interface System Clock FPGA Device FPGA Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Tim Price
    • 1
  • Cameron Patterson
    • 2
  1. 1.Xilinx Inc.OntarioCanada
  2. 2.Xilinx Inc.BoulderUSA

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