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Dynamically Reconfigurable Cores

  • John MacBeth
  • Patrick Lysaght
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

Dynamic reconfiguration of digital circuits on FPGAs has been an area of active research for the past decade. The identification of generic classes of circuits that would benefit from being dynamically reconfigured remains a key, open problem. We report on an investigation of the application of dynamic reconfiguration to programmable, multi-function cores (PMCs). An abstract analysis of the technique is included to emphasise the generality of the methodology. Empirical results for a case study involving a universal asynchronous receiver and transmitter (UART) are presented. We show that significant improvements in area efficiency and the operating speeds of the circuits are achieved. Furthermore, the results indicate the potential for reducing the power consumption of the circuits.

Keywords

Area Reduction Dynamic Reconfiguration Field Programmable Logic Reconfigurable Design Reconfigurable Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    P. W. Foulk, “Data-folding in SRAM Configurable FPGAs”, in IEEE Symposium on Field Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (Eds.), pp 163–171, Los Alamitos, California, April 1993Google Scholar
  2. [2]
    P. Lysaght, J. Stockwood, J. Law and D. Girma, “Artificial Neural Network Implementations on a Fine-Grained EPGA”, in Field Programmable Logic and Applications, R. Hartenstein, M. Z. Servit (Eds.), pp 421–431, Prague, Czech Republic, Sept. 1994Google Scholar
  3. [3]
    G. Brebner and J. Gray, “Use of Reconfigurability in Variable-length Code Detection at Video Rates”, in Field Programmable Logic and Applications, W. Moore and W. Luk (Eds.), pp 429–438, Oxford, England, Sept. 1995Google Scholar
  4. [4]
    M. J. Wirthlin and B. L. Hutchings, “DISC: The Dynamic Instruction Set Computer”, in Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, J. Schewel (Ed.), Proc. SPIE 2607, pp 92–103, Philadephia, PA, USA, Oct. 1995Google Scholar
  5. [5]
    H. Eggers, P. Lysaght, H. Dick and G. McGregor, “Fast Reconfigurable Crossbar Switching in FPGAs”, in Field Programmable Logic and Applications, R. Hartenstein and M. Glesner (Eds.), pp 297–306, Darmstad, Germany, Sept. 1996Google Scholar
  6. [6]
    W. Luk, N. Shirazi, S. Guo and P.Y.K. Cheung, “Pipeling Morphing and Virtual Pipelines”, in Field Programmable Logic and Applications, W. Luk, P. Cheung and M. Glesner (Eds.), pp 111–120, London, England, Sept. 1997Google Scholar
  7. [7]
    A. Donlin, “Self-modifying Circuitry — A Platform for Tractable Virtual Circuitry”, in Field Programmable Logic and Applications, R. Hartenstein and A. Keevallik (Eds.), pp 199–208, Tallinn, Estonia, Sept. 1998Google Scholar
  8. [8]
    G. McGregor and P. Lysaght, “Self Controlling Dynamic Reconfiguration: A Case Study”, in Field Programmable Logic and Applications, P. Lysaght, J. Irvine and R. Hartenstein (Eds.), pp 144–154, Glasgow, Scotland, Aug. 1999Google Scholar
  9. [9]
    Triscend Corporation, “Triscend A7 Configurable System-on-Chip Family”, Datasheet, http://www.triscend.com, Aug. 2000
  10. [10]
    Altera Corporation, “ARM-Based Embedded Processor Device Overview Data Sheet”, http://www.altera.com, Sept. 2000
  11. [11]
    Xilinx Inc., “IBM and XILINX to Create New Generation of Integrated Circuits”, Press Release, http://www.xilinx.com/prs_rls/ibmpartner.htm, July 2000
  12. [12]
    National Semiconductor Corporation, “PC16550D UART with FIFOs”, Datasheet, http://www.national.com/pf/PC/PCl6550D.html, June 1995
  13. [13]
    Texas Instruments Inc., “TIR2000 Data Manual: High-Speed Serial Infrared Controller With 64-Byte FIFO”, Data Manual, June 1998Google Scholar
  14. [14]
    A. M. Rincón, C. Cherichetti, J. A. Monzel, D. R. Stauffer and M. T. Trick, “Core Design and System-on-a-Chip Integration”, in IEEE Design & Test of Computers, Volume: 14 Issue: 4, pp 26–35, Oct.–Dec. 1997CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • John MacBeth
    • 1
  • Patrick Lysaght
    • 1
  1. 1.Dept. Electronic and Electrical EngineeringUniversity of StrathclydeGlasgowUK

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