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Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing

  • Albert Simpson
  • Jill Hunter
  • Moira Wylie
  • Yi Hu
  • David Mann
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

This paper describes the successful implementation of a hardware demonstrator for real-time JPEG standard colour image compression and decompression at picture refresh rates up to 25 frames per second using an FPGA-centric processing platform and design-reusable application-specific IP cores. The FPL device programming netlists for both JPEG encode and decode are directly derived from commercially available semiconductor Intellectual Property (IP Core) designs for Motion-JPEG applications; the target FPL devices form the core processing element in a commercial off-the-shelf reconfigurable module-based hardware platform for DSP and image processing applications. Performance metrics are presented for Xilinx Virtex and Altera APEX devices, and compared with semicustom ASIC implementations.

Keywords

Joint Photographics Expert Group Speed Grade Joint Photographics Expert Group Image Compress Image Data Variable Length Decoder 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Albert Simpson
    • 1
  • Jill Hunter
    • 1
  • Moira Wylie
    • 1
  • Yi Hu
    • 1
  • David Mann
    • 1
  1. 1.Amphion Semiconductor Ltd.Northern IrelandUK

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