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A n-Bit Reconfigurable Scalar Quantiser

  • Oswaldo Cadenas
  • Graham Megson
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

A reconfigurable scalar quantiser capable of accepting n-bit input data is presented. The data length n can be varied in the range 1... N-1 under partial-run time reconfiguration, p-RTR. Issues as improvement in throughput using this reconfigurable quantiser of p-RTR against RTR for data of variable length are considered. The quantiser design referred to as the priority quantiser PQ is then compared against a direct design of the quantiser DIQ. It is then evaluated that for practical quantiser sizes, PQ shows better area usage when both are targeted onto the same FPGA. Other benefits are also identified.

Keywords

Field Programmable Gate Array Systolic Array Scalar Quantiser Comparator Design FPGA Resource 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Oswaldo Cadenas
    • 1
  • Graham Megson
    • 1
  1. 1.Department of Computer ScienceUniversity of ReadingReadingUK

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