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Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders

  • Shervin Sheidaei
  • Hamid Noori
  • Ahmad Akbari
  • Hosein Pedram
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)

Abstract

The Global System for Mobile (GSM) communications uses a 13Kbps vocoder which expands to 22.8Kbps after channel coding. To increase the user capacity the half-rate channel has a gross transfer rate of 11.4Kbps. The vocoder for the half-rate channels operates at 5.6Kbps. To obtain better performance, GSM introduced enhanced full-rate vocoder which operates at 12.2Kbps. The computational requirements of these vocoders require the design of an entirely new digital signal processing architecture geared towards 1-D signal and speech processing. In this paper, at first the architecture of a specific design for full-rate vocoder is introduced, then according to the results of this architecture and common features available in all three vocoders, a DSP Core for implementing these vocoders is suggested. The architecture of the DSP Core is characterized by pipelining and parallel operation of functional units. This Core is a 16-bit fixed-point processor implemented on an FPGA and can be used as a real-time GSM vocoder.

Keywords

Functional Unit Stage Pipeline Primitive Function Speech Codec VLIW Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Shervin Sheidaei
    • 1
  • Hamid Noori
    • 2
  • Ahmad Akbari
    • 1
  • Hosein Pedram
    • 2
  1. 1.Computer Engineering DepartmentIran University of Science and TechnologyIran
  2. 2.Computer Engineering DepartmentAmirKabir University of TechnologyIran

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