A New Placement Method for Direct Mapping into LUT-Based FPGAs

  • Joerg Abke
  • Erich Barke
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2147)


In this paper, we present a new placement method which provides short implementation times for today’s high capacity FPGAs within a direct mapping environment. We show that using additional component information is beneficial for faster logic block placement. The new placement method reduces the placer’s run time by taking the module in- and output interconnections into account.


Minimum Span Tree Direct Mapping Logic Block Placement Algorithm Placement Method 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Joerg Abke
    • 1
  • Erich Barke
    • 1
  1. 1.Institute of Microelectronic Circuits and SystemsUniversity of HannoverHannoverGermany

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